Simulink® style modeling in your circuit design environment
Your system design has models in Simulink®, your circuit designs are in SPICE, and your verification engineers need Verilog-AMS models. How do you bridge the system to circuit level gap? Let Lynguent show you how with the System Level Toolkit™ for the ModLyng™ integrated modeling environment. This powerful capability enables you to use Simulink®-style system level model blocks in your current circuit design environment.
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By using Simulink® equivalent model building block in Modlyng you can: |
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Migrate your Simulink® system level designs.
This methodology is valuable for both SoC Design and SoC Verification
Migrate your Simulink® system level designs
Existing Simulink® designs may be easily migrated to your circuit design simulator through use of the ModLyng emulation libraries. All ModLyng Simulink® blocks are designed to be pin/parameter compatible with their Simulink® counterparts, so no conversions or “fudge factors” are required.
 Modeled in Simulink®... |
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 ...Modeled in ModLyng = 1:1! |
Equations and expressions may be easily entered using the ModLyng equation navigators and declarations editors; Constants, functions and parameters are all at your finger tips!
The ModLyng Equation Editor allows you to easily compose expressions and declarations with rapid access to standard language features.
Once the models have been migrated, it is simple to evaluate them in your target simulation environment, such as Cadence, Mentor® or Synopsys® tools.
Create high level signal-flow models
The Simulink® emulation libraries may be used exclusively or combined with other ModLyng libraries and user created content to compose high-level signal-flow type models which simulate in your Verilog-AMS/VHDL-AMS circuit design simulator.
The library navigator provides simple navigation of provided and user-defined models and effects
Its as simple as point and click; ModLyng automatically detects any and all type mismatches, undeclared parameters and invalid variable names as you create behavior; no need to execute the simulator to perform a syntax check-ModLyng models are always syntactically correct!
ModLyng automatically checks net and port types as you compose!
Compose complex analog stimulus
More than simply composing models, ModLyng and the System Level Toolkit allow you to compose reusable stimulus for any level of model abstraction, from transistor-level all the way up to system architecture.
Use stimulus to rapidly evaluate your model using the available stimulus sources and math operations. You can even reuse the stimulus to drive your transistor-level design
Stimulus model with electrical pins ready for use in any supported simulator.
Since ModLyng makes composing stimulus as a new model so simple, extend your test benches even further with analog assertions.
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Analog assertions can be used to measure performance without measuring waveforms!
Descend directly into circuit level implementation
The power of the ModLyng environment is that you’re never limited to any single modeling style or domain. Thus system-level signal flow models may be replaced in whole or part with behavioral or even circuit-level models.
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Easily mix signal-flow modeling with SPICE and behavioral models through signal attribute effects.
The above example replaces part of an active Simulink®-style 2nd order filter with an RLC equivalent composed from the ModLyng SPICE compatibility library.
Manage the design within the circuit design environment
ModLyng may be as a stand-alone modeling environment or may be tightly integrated with your circuit design environment, such as Cadence DFII with our CDSLynk product.
As an example: with ModLyng and CDSLynk, you can manage your ModLyng views and exported HDL views using the design framework and Cadence Library Manager, or directly from within ModLyng’s Library Navigator.
- ModLyng is connected to Cadence via CDSLynk
- The model is copied into the Cadence library
- Once there, the model can be exported from ModLyng into the Cadence HDL cellviews
- To save time, Cadence Symbol can be automatically generated as well
Manage your modeling effort with ModLyng and the Cadence IC Design Framework™ with CDSLynk™
Export the models to one of the standard HDL languages
ModLyng models may be exported as syntactically perfect HDL for your simulator, including Verilog-A, Verilog-AMS and VHDL-AMS, making simulation simple. This capability may be used to simultaneously support ONE model in MULTIPLE simulators and languages!
Simulate the design in your existing AMS simulator
ModLyng also incorporates a simulation plugin which may be customized to any HDL compliant simulator. This allows you to evaluate models and designs without ever leaving the IME.
Evaluate your models without ever leaving the IME! ModLyng can be integrated with the simulator and waveform tool of your choice.
With simulate plugin and configuration for your simulator (Cadence Spectre™ shown) simulation is one click away. Results are automatically presented in the waveform viewer of choice (Cadence Wavescan™ shown).
By bridging system level design and circuit level implementation within your existing design environment, Lynguent® enables your design team to create reliable designs with complete confidence that they have been verified to meet your customers’ specifications, and do so in a shorter amount of time.