Event Driven Mixed Signal Modeling

Situation: You're the verification engineer responsible for taping out a System-on-Chip (SoC), or maybe a chip set for a system in package (SiP), and the schedule is slipping. The digital teams are reaching timing closure and the analog teams are plowing through top level routing. Somehow you have to prove all these concurrent designs will work together.

What do you do?

Door Number 1

Merge the designs into one massive schematic and run fast spice.  The problem is that not all the designs are complete so you don’t have a complete SPICE netlist.  And even with all the speed of the fast spice simulator you are looking at a 3 week simulation.

Door Number 2

Evaluate your design with two simulators in box.  Create AMS models for the missing pieces and co-simulate with the RTL.  The simulations take only a few days to simulate but the experiment takes a week to configure, extract, and elaborate.

Door Number 3

Lynguent® can help you open Door Number 3. Simulate your analog blocks in a digital simulator.  Use Lynguent’s Event Driven Mixed Signal toolkit to rapidly compose real number models of your analog blocks and verify your SoC architecture.  Get ahead of the design curve on block level interactions with simulations that take minutes instead of weeks or days.  Capture waveforms and re-use them as analog stimulus for the lower level analog blocks where spice simulations are tractable. Validate your event driven analog model against the circuit using the same test bench and waveform viewers you are using today.

By using ModLyng's Event Driven Mixed Signal tools, you can:

Make fast models faster. Pull in your verification schedule by using Lynguent’s extensive Event Driven Mixed Signal tools to quickly compose analog behaviors that simulate at digital speeds.
Deliver analog models to digital engineers. Your analog systems and circuit design engineers can now deliver VHDL models to the digital design team without being VHDL experts. So go ahead, grab this month’s edition of EE Times and skip your VHDL training class.
Verify your supply domain functionality. Add supply sensitivity to your RTL to catch interactions of your digital and analog blocks during power up and power down sequencing.
Merge your analog and digital test benches. Use ModLyng™ to create and configure test benches that include RTL and Event Driven Analog Models.   See how your RTL interacts with the analog portion your SoC architecture before you commit resources to either digital synthesis or analog circuit design.
Cross-pollinate your system and block level stimulus. Use ModLyng’s signal capture tools to replay key Event Driven Analog results in your SPICE level simulations and your replay SPICE level results in your digital simulator.
Manage your simulation plan. Use ModLyng to manage the complexity of your SoC both in composition and configuration. Create dozens of simulation experiments from the same test bench.

This methodology is valuable for both SoC Design and SoC Verification.

 

Make Fast Models Faster

Quickly compose models from effects from Lynguent’s Event Driven Mixed Signal tools.  Add effects such as saturation, gain, filtering, voltage and current bias sensitivity to create a pin-accurate functional description of your analog design. Easily add assertions to log the status of key start up signals such as voltage biases, current bias and supply values.

The result is a blazingly fast model that simulates in a digital simulator, with all the key analog functional behaviors to check out your system. The transistor level simulation can take hours, but the Event Driven Analog model covers the same ground in seconds.

 

Deliver Analog Models to Digital Engineers

Let your analog systems and circuit design engineers deliver their Event Driven Analog models in VHDL. Sounds crazy right? With ModLyng the VHDL expertise is always present behind the scenes taking care of the VHDL ports, variables, types, libraries, packages, and all the other stuff you can spend a week learning in a VHDL training class.  Your analog designer can quickly compose an Event Driven Analog model, export it to VHDL, and email it to the systems integrator or digital design team ready-to-simulate in their digital design tools

 

Verify Your Supply Domain Functionality

Improve the fidelity of both your Event Driven Analog models and your digital models by adding supply domain sensitivity effects.  This allows you to verify the connectivity and functionality of the SoC supply domains even though you are plugging away in a digital simulator.

 

Merge Your Analog And Digital Test Benches

File based composition of coherent digital and analog stimulus can be cumbersome and highly error prone.  With Lynguent’s Event Driven Mixed Signal Stimulus tools you can easily merge analog and digital stimulus in one test bench. Using Lynguent’s simulator plug-ins you can seamlessly assemble, compose, and analyze your Event Driven Analog Stimulus.

 

Cross-Pollinate Your System and Block Level Stimulus

Want to re-use SPICE waveforms as stimulus in your Event Driven Analog test bench? No problem. What to re-use Event Driven Analog waveforms in your SPICE simulations? Please do. With ModLyng’s Event Driven Analog Signal Replay tools moving stimulus to and from the digital and analog simulation flows is as easy as drag and drop.

 

Manage Your Simulation Plan

Got complexity? Let ModLyng’s configuration editor map your SoC design.  Move fluidly through your SoC architectures and intelligently scale the design your verification experiments.  Create dozens of experiments using the same test bench with different levels of abstraction. Export your experiments and launch Event Driven Analog simulations on your digital simulator using ModLyng’s simulator plug-ins.  Deliver self-contained experiments across your digital design teams without the hassles common to managing VHDL libraries.

 

 

Interested in learning more? Register for a free on-line webinar and demo on how to efficiently leverage ModLyng to simulate your analog blocks in a digital simulator.