Migration from Simulink® Level Design to Physical Implementation
Lynguent’s methodology to migrate system level models developed in Matlab®/Simulink into a Verilog-A, Verilog-AMS or VHDL-AMS description bridges the gap between system level and physical design of analog and mixed systems. It will also allow you to simulate portions of the transistor level design along with portions of the system level design in your HDL simulator. The methodology uses proven HDL representations for the standard Simulink analog blocks and custom models for user-written primitives. Lynguent also provides services to migrate specific designs from Simulink to HDL.

VHDL Real Number Modeling — allows analog blocks to run in digital simulator

Using Lynguent’s methodology, the efficiency of our tools, and  reduced dependence on HDL expertise, we have put the power of real number modeling into the hands of AMS verification engineers. By abstracting the AMS behavior into a digital block, verification engineers can run the models of AMS chips in digital simulators  which reduces simulation time up to factor 1000. This enables both more simulation runs as well as running existing tests for a longer time.