ModLyng is the first integrated modeling environment for analog / mixed signal models. It provides you with an array of tools to create, enhance, debug, validate, and translate your AMS structural and behavioral models.

You can start with an existing model written in a popular analog hardware description language (HDL) -- including Verilog-A, Verilog-AMS and VHDL-AMS, -- or create a behavioral model from scratch by graphically adding ports, circuit branches, and other building blocks, and then provide the model and branch equations. Either way, you get a validated model faster than ever before, and you do not even have to write code in your HDL!

ModLyng includes several interlinked editors to help you create, debug, and manage even very complex AMS models. The graphics show the Model Navigator, the Topology Editor, the Equation Editor, the Model Interface Editor, and the Graph tool.

The Model Information Editor shows you the model, connection (port), and parameter information that was distilled from your imported model or that you created via the Topology editor.

The Topology Editor graphically represents your model. You can view and modify your model's structure just as you would manage your design with a schematic entry system. You simply place model branches (as shown), building blocks, connections, and terminals in the editor. The Equation Editor then lets you describe the behavior of each symbol.

With the Equation Editor you provide a complete mathematical description of the model. The equations can be extracted from the original language of your model. You can add or modify the equations, and ModLyng will check the validity of your equations.

Once you have created, debugged, and validated your model with ModLyng, you can generate it in the language of your choice, be it Verilog-A/AMS, or VHDL-AMS.. ModLyng maintains its own representation based on an industry standard, and you can create multiple versions of your model without redoing any of your work.