ModLyng™ Design and Verification Studio for Event-Driven Mixed-Signal

The ModLyng DV Studio for EDMS targets the development of analog and AMS parts and subsystems to be used in a digital flow. Such real number models use wreal ports in Verilog and real signal ports in VHDL and can be simulated in all popular Verilog-AMS and VHDL simulators. Using event-driven techniques, such models simulate two to three orders of magnitude faster than AMS models for the same device.