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Languages and Dialects in the ModLyng Integrated Modeling Environment

The ModLyng™ Integrated Modeling Environment allows users to compose models in a language independent way. Once complete, a model can be exported to a file containing a representation of the model in one of the following hardware description languages:

  • Verilog-A
  • Verilog-AMS
  • VHDL-AMS
  • MAST

Purely analog models can be exported to any of these languages, while mixed-signal models can be exported to either Verilog-AMS or VHDL-AMS. Conversely, models written in any of these languages may be imported into the ModLyng IME.

To accommodate simulators and other tools that support different subsets of these languages, the ModLyng IME provides a variety of language dialects. As an example, a model isn't just exported to Verilog-A, but to a specific dialect of Verilog-A. Similarly, language import is dialect specific. The 1.3.2 release of the ModLyng IME supports the following dialects:

  • Verilog-A
    • Verilog-A OVI 1.0, corresponding to the Verilog-A language specification V1.0 published by Open Verilog International. See http://www.vhdl.org/verilog-ams/htmlpages/lit.html.
    • Verilog-A ADMS 2.2.8, a dialect that supports the ADMS code generator that converts a Verilog-A compact model to a C-language model. See http://mot-adms.sourceforge.net for further information.
    • Verilog-A Spectre 5.1, a dialect that supports the version 5.1 of the Cadence® Spectre® simulator. See www.cadence.com.
    • Verilog-A Spectre 6.1, a dialect that supports the versions 6.x, 7.x, and later of the Cadence Spectre simulator. See www.cadence.com.
    • Verilog-A for Hspice 2008.9, a dialect that supports the version 2008.9 of the Synopsys Hspice simulator. See www.synopsys.com.
  • Verilog-AMS
  • VHDL-AMS
    • VHDL IEEE 1076.1-1999, corresponding to the VHDL-AMS language specification defined by IEEE Std 1076.1-1999 IEEE Standard VHDL Analog and Mixed-Signal Extensions. You can get this standard at http://shop.ieee.org.
  • MAST

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